An 8 Gb/s–64 Mb/s, 2.3–4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS Mrunmay Talegaonkar, Student Member , IEEE ,A m r E l s h a z l y, Member , IEEE, Karthikeyan Reddy, Student Member , IEEE , Praveen Prabha , Student Member , IEEE , Tejasvi Anand, Student Member , IEEE, and Pavan

Abstract

A burst-mode transmitter a chieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. The resistor tuning-based ring oscillator avoids the use of bias voltages and thereby eliminates the related settling time overhead. The calibrated rapid on-off biasing circuit utilizes a fast charging technique to achieve bias voltage settling time of 4 ns, res ulting in 30X improvement over a diode-connected bias circuit. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy ef ficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in ef- fective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy ef ficiency for 32 byte long data bursts. We also present an analytical bit error rate (BER) computation technique for rapid on-off links, which uses MDLL settling measurement data in conjunction with always-on transmitter measureme nts. This technique indicates that the BER bathtub width for 10 BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation , respec- tively.