A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Ampli fier Linfei Guo

Abstract

Present-day smartph ones and tablets demand high audio fidelity (e.g., total harmonic distortion + noise, THD + N 0.01%), and high noise immunity (e.g., power supply rejection ratio, PSRR 80 dB) to allo w high integration in an SoC. The design of conventional closed-loop pulse width modulation (PWM) Class-D ampli fiers (CDAs) typically involves undesirable trade-offs between fidelity (quali fie db yT H D+N ) ,P S R Ra n d switching frequency. In this pape r, we propose a fully integrated CMOS CDA that embodies a novel i nput-modulated carrier gen- erator and a novel pha se-error-free PWM modulator, collectively allowing the employment of high loop-gain to achieve high PSRR, yet without compromising linearity/dynamic-range or resorting to high switching f requency. The prototype CDA, realized in 65 nm CMOS, achieves a THD + N of 0.0027% and a power ef ficiency of 94% when delivering 500 mW to an 8 Ω load from V =3 . 6V . The PSRR of the prototype CDA is very high, –101 dB @217 Hz a n d9 0d B@ 1k H z ,a r g u a b l yt h eh ighest to-date. Furthermore, the switching frequency of the prototype CDA varies from 320 to 420 kHz, p otentially reducing the EMI due to spread-spectrum. In addition, the prototype CDA is versatile with a large oper- ating-voltage range, with V ranging from rechargeable 1.2 V single battery to standard 3.6 V smart-device supply voltages.