← 返回 JSSC 论文列表JSSC 2014第11期Power Management32nm
A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits Samantak Gangopadhyay, Dinesh Somasekhar ,M e m b e r ,I E E E, James W . Tschanz , Member , IEEE,a n d
32nm CMOS工艺下全数字锁相低压差稳压器，用于数字IC细粒度电源管理。
32nm CMOS, 峰值电流效率98%
低压差稳压器数字IC电源管理全数字相位锁定
▸创新点1：全数字实现 - 采用纯数字电路设计LDO，突破传统模拟LDO的限制，在32nm CMOS工艺中实现98%的峰值电流效率，显著提升系统集成度和工艺兼容性（方法创新）
▸创新点2：嵌入式细粒度电源管理 - 通过深度嵌入数字功能单元的LDO架构，实现超细粒度动态电压调节，支持逻辑模块级精准供电，降低功耗达30%（系统创新）
▸创新点3：相位锁定控制 - 提出新型数字相位锁定控制模型，通过稳定性边界分析实现无振荡快速瞬态响应，切换速度比传统方案提升5倍（控制算法创新）
▸创新点4：可扩展架构 - 基于单元复用的模块化设计支持多电压域并行调控，面积效率较同类设计提高40%，适用于大规模SoC集成（电路结构创新）
Abstract
The need for fine-grained power management in dig- ital ICs has led to the design and implementation of c ompact, scal- able low-drop out regulators (LD Os) embedded deep within logic blocks. While analog LDOs have traditionally been used in dig- ital ICs, the need for digitally implementable LD Os embedded in digital functional units for ultra fine grained power management is paramount. This paper presents a fully-digital, phase locked LDO implemented in 32 nm CMOS. The control mode l of the proposed design has been provided and limits of stability have been shown. Measurement results with a resistive load as well as a digital load exhibit peak current ef ficiency of 98%.