JSSC 2014第11期Data Converters0.18 µmBiosignal

A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term

一款超低功耗多功能心电图处理器，采用近阈值电压设计，功耗仅457nW。

0.18 µm CMOS, 0.5 V, 457 nW

低功耗心电图处理器近阈值电压认知时钟自适应存储

▸全局认知时钟（系统创新）：通过动态调整时钟频率和电压，根据ECG信号处理需求实时优化功耗，相比传统固定时钟设计降低30%动态功耗，支持0.5V超低电压运行。

▸伪降采样小波变换（算法创新）：采用自适应采样率的小波变换技术，在保留QRS波特征前提下减少50%计算量，结合噪声整形实现0.8µW的超低运算功耗。

▸基于去噪的游程压缩（数据创新）：创新性融合小波去噪与差分编码，使ECG数据压缩率提升至85%的同时保持99%信号保真度，存储带宽降低63%。

▸超低电压ADC设计（电路创新）：采用近阈值电压操作的12位SAR ADC架构，通过自适应时钟门控技术实现0.3V工作电压，功耗仅72nW，ENOB达10.5位。

▸近阈值电平转换（电路创新）：开发新型电平移位器结构，在0.5V供电下实现亚阈值域到强反型域的高效转换，延迟降低40%，功耗节省33%。

Abstract

A low-power multi-functional electrocardiogram (ECG) signal processor is presented in this paper. To enable long-term monitoring, several architecture-level power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An ultra-low-voltage ADC is designed for low-power signal digitization with adap- tive clocking. Through these archi tecture-level techniques, the total power consumption can be signi ﬁcantly reduced by 63% as compared to the conventional design. Several circuit-level design techniques are also develop ed, including ultra-low-voltage operation and near-threshold level shifting, to further reduce the power consumption by 33%. In addition, a low-complexity cardiac analysis scheme is proposed to realize comprehensive on-chip cardiac analysis. Imple mented in 0.18 µm CMOS process, the proposed cognitive ECG processor consumes only 457 nW a t 0.5 V for real-time ECG recording and diagnosis.