A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver

Abstract

High-speed ADC front-ends in wireline receivers allow for implementing flexible, complex, and robust equalization in the digital domain, as well as easily supporting bandwidth-ef fi- cient modulation schemes, such as PAM4 and duobinary. However, the power consumption of these ADC front-en ds and subsequent digital signal processing is a major issue. This paper presents a 64-way 6 bit 10 GS/s time-interleaved successive-approxima- tion-based ADC front-end that ef ficiently incorporates a two-tap embedded FFE and a one-tap embedded DFE, providing the potential for a lower complexity back-end DSP and/or decreased ADC resolution. Fabricated in a 1. 1V GP 65nm CMOS process, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33 mm 2 core ADC area. The effectiveness of t he embedded FFE and DFE is demonstrated with signi ficant timing margin improvement observed for 10 Gb/s operation over several FR4 channels.