← 返回 JSSC 论文列表JSSC 2014第11期RF & WirelessSAR ADCDAC
A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode
提出一种采用数字校正技术的全集成SAR ADC，适用于三模收发器。
52 MS/s时SNDR 67.0 dB (GSM), 80 MS/s时58.2 dB (WCDMA/LTE)
SAR ADC数字校正多模收发器电荷共享非二进制DAC
▸非二进制DAC结构：采用非二进制DAC结构实现更高的线性度和更低的功耗，通过优化权重分配减少了比较器次数，在52 MS/s和80 MS/s采样率下分别实现67.0 dB和58.2 dB的SNDR。
▸数字校正技术：引入数字校正技术有效补偿了DAC失配和比较器偏移，提升了ADC的整体精度，特别是在多模式操作下保持稳定的性能。
▸电荷共享拓扑消除参考电压片外电容：通过创新的电荷共享拓扑结构，完全消除了对外部参考电压去耦电容的需求，显著减小了芯片面积（核心面积仅0.044 mm²）。
▸可配置多模式操作：通过动态调整ADC速度和噪声特性，支持GSM/WCDMA/LTE三种模式的无缝切换，在不同采样率下均保持优异的信噪比性能。
Abstract
This paper presents a fully integrated SAR ADC for GSM/WCDMA/LTE triple-mode transceiver (R FIC) with non-binary DAC structure and digital correction techniques. All blocks including input buffer, ADC core, bias, references and ADC logics are implemented in a single chip with a small die area of 0.044 mm /0.066 mm for ADC core and ADC logic. The proposed ADC does not require off-chip decoupling capacitor for reference voltage by employing charge-sharing topology. Recon figurable structure is used for multi-mode operation by adjusting ADC speed and noise, where SNDR of 67.0 dB in GSM and 58.2 dB in WCDMA/LTE are achieved at the sam pling frequencies of 52 MS/s and 80 MS/s, respectively.