A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Y asuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, and Y asunori Tanaka

Abstract

An extremely low-power flip-flop (FF) named topo- logically-compressed flip-flop (TCFF) is proposed. As compared with conventional FFs, the FF reduces power dissipation by 75% at 0% data activity. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression method, merger of logically equivalent transistors to an unconventional latch struc- ture. The very small number of transistors, only three, connected to clock signal reduces the power drastically, and the smaller total transistor count assures the same cell area as conventional FFs. In addition, fully static full-swing operation makes the cell tolerant of supply voltage and input slew var iation. An experimental chip design with 40 nm CMOS technology shows that almost all con- ventional FFs are replaceable wi th proposed FF while preserving the same system performance and layout area.