An 8–16 Gb/s, 0.65–1.05 pJ/b, V oltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning Y

Abstract

Serial link transmitters which ef ficiently incorporate equalization, while also enabling fast power-state transitioning to leverage dynamic power scaling, are necessary to meet fu- ture systems’ I/O requirements. This paper presents a scalable voltage-mode transmitter which offers low static power dissipa- tion and adopts an impedance-modulated 2-tap equalizer with analog tap control, thereby obviating driver segmentation and reducing pre-driver complexity and dynamic power. Topologies that allow for rapid power-up/down, including a replica-biased voltage regulator to power the output stages of multiple transmit channels and per-channel quadrature clock generation with injection-locked oscillators (ILO), enable fast power-state transi- tioning. Energy ef ficiency is further improved with capacitively driven low-swing global clock distribution and supply scaling at lower data rates, while output eye quality is maintained at low voltages with automatic phase calibration of the local ILO-gen- erated quarter-rate clocks. A pr ototype fabricated in a general purpose 65 nm CMOS process includes a 2 mm global clock distribution network and two tra nsmitters that support an output swing range of 100–300 mV with up to 12 dB of equalization. The transmitters achieve 8–16 Gb/s operation at 0.65–1.05 pJ/b energy efficiency and sub-3 ns power-up/down times.