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Comments and Corrections Correction to “Recon figurable Processor for Energy-Efficient Computational Photography” Rahul Rithe, Priyanka Raina, Nathan Ickes, Srikanth Tenneti, and Anantha P . Chandrakasan In the above paper [1], an error was made in reporting the operating voltage for the SRAMs. Section V I of the paper states: “The test chip, shown in Fig. 19, is implemented in 40 nm CMOS technology and Manuscript received August 17, 2 014; accepted August 23, 2014. Date of publication September 16, 2014; date of current version October 24, 2014.
论文更正了SRAM工作电压的错误报告。
40nm CMOS, 0.5V to 0.9V, 25MHz to 98MHz
SRAM工作电压40nm CMOS处理器更正
▸创新点1：更正SRAM工作电压的错误（方法创新）：通过详细的技术审查和验证，修正了原论文中关于SRAM工作电压的错误描述，确保了数据的准确性和可靠性。
▸创新点2：澄清处理器与SRAM共享同一电源电压（系统创新）：明确指出处理器和SRAM在同一芯片上共享同一电源电压，避免了读者对系统设计的误解，提升了系统设计的透明度。
▸创新点3：感谢同事发现错误（方法创新）：公开感谢同事Arun Paidimarri和Mehul Tikekar发现并指出错误，体现了学术合作和严谨的科学态度，促进了学术界的诚信和合作精神。
Abstract
Priyanka Raina, Nathan Ickes, Srikanth Tenneti, and
Anantha P . Chandrakasan
In the above paper [1], an error was made in reporting the operating
voltage for the SRAMs. Section V I of the paper states: “The test chip,
shown in Fig. 19, is implemented in 40 nm CMOS technology and
Manuscript received August 17, 2 014; accepted August 23, 2014. Date of
publication September 16, 2014; date of current version October 24, 2014.
R. Rithe, P. Raina, N. Ickes, and A. P. Chandrakasan are with the Micro-
s