Design of a Temperature-Aware Low-V oltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C Tony

Abstract

This paper presents an 8-Kbit low-power SRAM for high-temperature (up to 300 °C) applications. For reliable low-voltage operation, we employed a decoupled 8T SRAM cell structure. To minimize the performance variations caused by the wide operating temperate range, supply voltage was selected in the near-threshold region. A tem perature-aware bitline sensing margin enhancement technique is proposed to mitigate the impa ct of signi ficantly increased bitline leakage on bitline swing and sensing window. A temperature-tracking control circuit gener- ates bias voltage for optimal pull-up current for real izing the proposed enhancement technique. Test chips were fabricated in a commercial 5 V , 1.0 µm SOI techno logy. Test chip measurement demonstrates successful operation down to 2 V at 300 °C. The average energy of 0.94 pJ was achieved at 2 V and 300 °C.