Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback

Abstract

Single-bit continuous-time delta-sigma modulators (CTDSM) using FIR feedback DACs inherit the appe aling aspects of both single-bit and multibit designs, without the disadvantage of either approaches. In this work, w eg i v eam e t h o df o rs t a b i l i z i n g a CTDSM that uses an FIR feedback DAC. Further , we show that increasing the number of taps beyond a certain number (dependent on the architecture and oversampling ratio of the modulator) does not improve performance. The results of our analysis are incorpo- rated in the design of a third-order audio CTDSM which achieves a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a spurious-free dynamic range of 106 d B in a 24 kHz bandwidth, while consuming only 280 µW from a 1.8 V supply.