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A1 4B i t1G S / sR FS a m p l i n gP i p e l i n e dA D C With Background Calibration Ahmed M. A. Ali , Member , IEEE, Huseyin Dinc
14位1GS/s RF采样流水线ADC，采用背景校准技术提升性能
65nm CMOS, 140MHz 2Vpp输入时SNR 69dB, SFDR 86dB, 功耗1.2W
ADCRF采样背景校准流水线非线性补偿
▸创新点1：基于相关性的背景校准技术（方法创新） - 该技术通过实时监测和校正级间增益、建立时间和记忆误差，显著提升了ADC的动态性能和线性度，支持14位精度和1 GS/s采样率。
▸创新点2：输入失真消除技术（电路创新） - 通过优化输入驱动电路和采样电容设计，有效抑制了非线性失真，提高了RF采样性能，实测SFDR达到86 dB。
▸创新点3：数字背景校准补偿非线性电荷注入（系统创新） - 采用数字校准算法动态补偿采样电容的非线性电荷注入（kick-back），降低了输入驱动器的负担，提升了整体系统稳定性。
▸创新点4：嵌入式有效抖动技术（方法创新） - 在校准信号中嵌入抖动，打破了校准收敛对输入信号幅度的依赖，确保了校准过程的一致性和可靠性。
Abstract
We discuss a 14 bit 1 GS/s RF sampling pipelined ADC that utilizes correlation-based background calibration to correct the inter-stage gain, settling and memory errors. To im- prove the sampling linearity an d RF sampling performance, the ADC employs input distortion cancellation and a digital back- ground calibration technique to compensate for the non-linear charge injection (kick-back) fr om the sampling capacitors on the input driver. In addition, an effective dithering technique is embedded in the calibration sign al to break the dependence of the calibration’s convergence on the input signal amplitude. The ADC is fabricated on a 65 nm CMOS process and has an integrated input buffer. With a 140 MHz and 2 Vpp input signal, the SNR is 69 dB, the SFDR is 86 dB, and the power is 1.2 W.