A6 9 . 5m W2 0G S / s6 bT i m e - I n t e r l e a v e dA D C With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI

Abstract

A 20 GS/s 6b time-interleaved ADC is implemented in 32 nm CMOS SOI with an embedded time-to-digita l converter to sense timing skew, and the rand omness of process mismatch is exploited to compensate for the c lock misalignment and dynamic offset errors of comparators that occur durin g high-speed opera- tion. To achieve low-power consumption at high-speed operation with small-size transistors, a low -complexity on-chip calibration reduces gain, offset, and delay mismatches in background. With the timing skew calibration, the spurs due to clock misalignment are reduced by 20 dB. The proposed ADC achieves an SNDR of 30.7 dB at Nyquist frequency and cons umes only 69.5 mW with a figure-of-merit of 124 J/conv-step.