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A 10 bit SAR ADC With Data-Dependent Energy Reduction Using LSB-First
提出一种LSB优先的逐次逼近算法，实现10位SAR ADC，显著降低低活动信号采样时的能耗。
0.18μm CMOS, 0.6V, 16kHz, 9.73b ENOB, 3.5-20fJ/conversion-step FoM
SAR ADC逐次逼近低功耗LSB-first能效优化
▸创新点1：LSB-first逐次逼近算法（方法创新）。该算法改变了传统SAR ADC的MSB-first策略，优先处理LSB，使得能耗和输入信号活动性对数相关，显著降低了低活动信号采样时的功耗。
▸创新点2：能耗与输入信号活动性对数相关（系统创新）。通过LSB-first算法，ADC的能耗和转换所需的bitcycles数随输入信号活动性对数变化，优化了低活动信号下的能效表现。
▸创新点3：低功耗设计适用于低活动信号采样（电路创新）。采用0.18 μm CMOS工艺和0.6V电源电压，实现了最低0.58 nW的泄漏功耗和3.5 fJ/conversion-step的最佳FoM，特别适用于低活动信号的应用场景。
▸创新点4：灵活的电源电压调节（系统创新）。支持电源电压从0.5V到1.0V的调节，能够在不同电压下实现2.9–17 fJ/conversion-step的FoM范围，适应多种采样率和能效需求。
Abstract
This paper presents a successive approximation (SA) algorithm called LSB-first SA and a corresponding 10 bit ADC im- plementation. The energy per conversion and number of bitcycles per conversion used by this algor ithm both scale logarithmically with the activity of the input signal, such that an N-bit conversion uses between 2 and 2N+1 bitcycles, compared to N for conven- tional binary SA. This algorithm reduces ADC power consump- tion when sampling signals with low mean activity. The ADC is implemented in a 0.18 μmC M O Sp r o c e s s .W i t ha0 . 6Vs u p p l y , the maximum sample rate, leak age power, and ENOB are 16 kHz, 0.58 nW, and 9.73 b, averaged over 10 test chips. The DNL and INL are bounded at 0.09 and 0.22 LSBs. Given a DC input, the ADC achieves its best-case FoM of 3.5 fJ/conversion-step. Given a fullscale Nyquist sinusoid input, the ADC has its worst-case FoM of 20 fJ/conversion-step. The supp ly voltage can be increased to 1.0 V to reach a sample rate of 450 kHz, or decreased to 0.5 V to achieve a 2.9–17 fJ/conversion-step FoM range.