JSSC 2014第12期Data Converters28nmSAR ADC

A 1.5 mW 68 dB SNDR 80 Ms/s 2 Interleaved Pipelined SAR ADC in 28 nm CMOS Frank van der Goes, Christopher M. Ward, Santosh Ast gimath, Han Y an, Jeff Riley, Zeng Zeng, Jan Mulder

本文介绍了一种28nm CMOS工艺下80 MS/s、11位ENOB的低功耗ADC。

28nm CMOS, 80 MS/s, 11 bit ENOB, 1.5 mW

低功耗SAR ADCCMOS流水线噪声滤波

▸创新点1：双交错流水线SAR ADC架构（系统创新）——通过两个交错流水线SAR ADC的并行工作，显著提高了采样速率和转换效率，同时降低了功耗，实现了80 MS/s的高采样率和11位ENOB的高精度。

▸创新点2：基于积分器的噪声滤波放大器（电路创新）——采用积分器作为噪声滤波放大器，有效降低了噪声干扰，提升了信号的信噪比（SNDR），达到了68 dB的高性能指标。

▸创新点3：改进的DAC切换方案（电路创新）——通过优化DAC的切换策略，减少了DAC切换过程中的能量消耗，进一步降低了整体功耗，使得总功耗仅为1.5 mW。

▸创新点4：片上参考电压生成器（系统创新）——集成片上参考电压生成器，无需外部组件，简化了系统设计，提高了系统的集成度和可靠性。

Abstract

This paper presents a power-ef ﬁcient 80 MS/s, 11 bit ENOB ADC. It is realized in 28 nm CMOS and is based on two interleaved pipelined SAR ADCs. I t includes an on-chip reference generator and does not require any external components. The total power dissipation is 1.5 mW, resu lting in a low-frequency Walden FOM of 9.1 fJ/conv-step and a low-frequency Schreier FOM of 172.2 dB, which is the largest FOM reported to date for sampling frequencies larger than 1 MS/s. The key aspects in achieving this excellent power ef ﬁciency include the choice of ADC architecture, integrator-based ampli ﬁers used for noise ﬁltering, the ﬁnite set- tling of the reference voltage during the SAR conversion, and the modiﬁed DAC switching scheme to reduce the DAC switching en- ergy.