A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Ampli fier Using Timing Alignment Technique for WCDMA and LTE Kazuaki Oishi, Eiji Y oshida, Y asufumi Sakai, Hideki Ta kauchi, Y oichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Y amazaki, and

Abstract

A fully integrated envelope elimination and restora- tion (EER) CMOS power ampli fier (PA) has been developed for WCDMA and LTE handsets. EER is a supply modulation technique that first divides modulated RF signal into envelope and phase signals and then restores it at a switching PA output. Supply voltage of the switching PA is modulated by the envelope signal through a high-speed supply modulator. EER PA is highly ef ficient due to the switching PA and the supply modulation. However, it generally has dif ficulty, especially for a wide bandwidth baseband application like LTE, achieving a wide bandwidth for phase signal path and highly accurate timing between envelope and phase sig- nals. To overcome these challenges, an envelope/phase generator based on a mixer and a limiter was proposed to generate the wide bandwidth phase signal, and a timing aligner based on a delay locked loop with a variable high-pass filter (HPF) was proposed to compensate for the timing mismatch. The chip was implemented in 90 nm CMOS technology. Measured power-added ef ficiency (PAE) and adjacent channel leakage ratio (ACLR) were 39% and –41 dBc for WCDMA, and measured PAE and ACLR E-UTRA1 were 32% and –33 dBc for 20 MHz-BW LTE.