A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing

Abstract

This paper presents a time-interleaved (TI) SAR ADC which enables background timing skew calibration without a sep- arate timing reference channel and enhances the conversion speed of each SAR channel. The proposed ADC incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Be- cause the full-speed flash ADC does not suffer from timing skew errors, the flash ADC output is also used as a timing reference to estimate the timing skew of the TI SAR ADCs. A prototype ADC is designed and fabricated in a 65 nm CMOS process. After back- ground timing skew calibration, 51.4 dB SNDR, 59.1 dB SFDR, and 1.0 LSB INL/DNL are achieved at 1 GS/s with a Nyquist rate input signal. The power consumption is 18.9 mW from a 1.0 V supply, which corresponds to 62.3 fJ/step FoM.