A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS Taegeun Y oo, Student Member , IEEE , Hong Chang Y eoh , Member , IEEE, Y un-Hwan Jung

Abstract

This paper presents a direct digital frequency syn- thesizer (DDFS) based on the nonlinear DAC with a ma ximum operating frequency of 2 GHz. Thi sw o r kp r o p o s e st h r e ed e s i g n methods to enhance the performance of a DDFS. First, a multi-level momentarily activated bias is proposed to reduce power dissipa- tion in the phase accumulator. S econd, a coarse phase-based con- secutive fine amplitude grouping scheme is presented to reduce hardware complexity and power consumpt i o ni nt h ed i g i t a ld e - coder. Third, the mixed-wave conv ersion topology in the nonlinear DAC is proposed to improve the output spectral purity. The DDFS with 9 bit amplitude resolution is capable of producing a minimum spurious-free dynamic range (SFDR) of 55.1 dBc up to Nyquist fre- quency at the clock frequency of 2 GHz. The prototype DDFS is fabricated in a 55-nm CMOS. It o ccupies an active area of 0.1 mm 2 with a total power dissipation of 130 mW. The figure of merit of this DDFS is 8944 GHz · 2 (SFDR/6)/W.