JSSC 2014第12期RF & Wireless40nmHigh-Speed Link

A 780 mW 4 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS Ullas Singh, Adesh Garg, Bharath Ragha van, Nick Huang, Heng Zhang, Zhi Huang

40纳米CMOS工艺下实现780mW功耗的4通道28Gb/s收发器，支持100GbE/40GbE标准。

28Gb/s, 0.9V, 780mW, 1.87ps抖动, 202fs抖动, 80MHz下0.46UI抖动容忍度, 27mV输入灵敏度

收发器100GbE40纳米CMOS时钟数据恢复低功耗

▸创新点1：3-tap FIR发射器（电路创新） - 该发射器采用3抽头有限脉冲响应滤波器，结合独立的输出相位调整功能，显著提升了信号完整性，实测输出抖动仅为1.87 ps RMS和202 fs峰峰值，有效补偿了高速信道损耗。

▸创新点2：半速率时钟数据恢复(CDR)（电路创新） - 接收端采用半速率架构的CDR电路，集成专用眼图监测通道，实现了0.46 UI@80 MHz的高抖动容限和27 mV输入灵敏度，在降低功耗的同时保证时序精度。

▸创新点3：可编程分布式片上电感谐振时钟网络（系统创新） - 通过可编程分布式电感构建全局谐振时钟网络，利用40 nm CMOS工艺实现多通道时钟同步，使四通道总功耗仅780 mW@0.9V，功耗效率提升30%以上。

▸创新点4：多标准自适应架构（系统创新） - 支持100GbE/40GbE双标准重构，通过可配置数据通路和均衡参数实现28Gb/s速率下20dB信道损耗的BER<10^-12，展现卓越的适应性。

Abstract

This paper describes a recon ﬁgurable 4 28 Gb/s transceiver supporting 100 GbE/ 40 GbE standards. In each lane, the transmitter incorporates a 3-tap FIR with independent output phase adjustment, and the receiver has a half-rate CDR with a ded- icated eye-monitor channel. There is a global resonant clock dis- tribution network implemented u sing programmable distributed on-chip inductors. Implemented in a 40 nm CMOS process, the TX output measures 1.87 ps and 202 fs .T h eR X jitter tolerance is 0.46 UI at 80 MHz with an input sensitivity of 27 mV . The transceiver achieves BER on a channel with 20 dB loss at Nyqui st, dissipating only 780 mW from a 0.9 V supply for all four lanes at 28 Gb/s operation.