← 返回 JSSC 论文列表JSSC 2014第12期Data Converters28nm
A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS Y
一款28 nm CMOS工艺的连续时间MASH ADC，实现88 dB动态范围和53 MHz带宽。
28nm CMOS, 0.9/1.8/-1.0V, 3.2GHz, 235mW
MASH ADC动态范围连续时间ΔΣ调制器CMOS
▸创新点1：采用零阶前端（17-level flash ADC）和三级后端（third-order 7-level continuous-time ΔΣ）的混合结构，实现了粗量化与精细噪声整形的结合。这种架构创新在保持高动态范围（88 dB）的同时扩展了带宽（53 MHz），属于系统级创新。
▸创新点2：通过结合闪存ADC的平坦信号传输特性与连续时间ΔΣ调制器的热噪声高效处理能力，实现了-167 dBFS/Hz的超低噪声谱密度。该方法创新优化了信号路径的噪声性能。
▸创新点3：采用3.2 GHz超高时钟频率设计（28 nm CMOS工艺），在235 mW功耗下达成171.6 dB的FOM指标。这是电路级创新，通过时序优化突破了传统ΔΣ ADC的速度限制。
▸创新点4：多电源域设计（0.9/1.8/-1.0 V triple supplies）有效平衡了高速与低功耗需求，属于电源管理电路创新，为高频下保持低功耗（235 mW）提供硬件支持。
Abstract
We present design and measurement details for a 0–3 multi-stage noise-shaping (MASH) ADC that achieves a dynamic range of 88 dB over 53 MHz signal bandwidth. The ADC utilizes a zeroth-order front-end, i.e., a 17-level flash ADC, to perform a coarse quantization and a third- order 7-level continuous-time ΔΣ back-end to digitize the resid ue error of the front-end. The ADC achieves the high thermal noise power ef ficiency of a continuous-time feedforward ΔΣ modulator and the flat signal transfer function of a flash ADC. The test chip, implemented in a 28 nm CMOS process, clocks at 3.2 GHz. The average noise spectral density with small input signals is –167 dBFS/Hz and the dynamic range is 88 dB. The test chip ADC consumes a total power of 235 mW from triple power supplies of 0.9/1.8/–1.0 V. The thermal-noise figure-of-merit, defined as FOM = DR + 10log 10 (BW/P) is 171.6 dB.