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A Low-Power, Low-V oltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS
提出一种低功耗低电压WBAN兼容的PSK接收器，采用数字密集型架构，适用于传感器网络。
65nm CMOS, 0.6V, 1.3mW, 91dBm/96dBm灵敏度
低功耗低电压WBANPSK接收器子采样
▸基于子采样的数字密集型架构：该方法创新性地采用数字密集型架构，通过子采样技术降低功耗（1.3 mW）和电压（0.6 V），同时兼容IEEE 802.15.6 WBAN窄带物理层规范，显著提升了接收器的能效。
▸Q增强技术：电路创新中引入Q增强技术，优化了接收器的灵敏度，在-DQPSK和-DBPSK调制下分别达到91 dBm和96 dBm的灵敏度，实现了低功耗高性能的平衡。
▸数字中频技术：系统创新中采用数字中频技术，减少了传统模拟中频的复杂性和功耗，同时通过数字信号处理提高了系统的灵活性和可扩展性，适用于超低功耗传感器网络。
▸低电压设计：通过电压缩放技术（0.6 V）和65 nm CMOS工艺，实现了3倍的能效提升和0.35 mm²的硅面积优化，为WBAN应用提供了高集成度和低成本的解决方案。
Abstract
A PSK receiver (RX) is proposed that employs a digital-intensive architecture based on sub-sampling, Q-enhance- ment, and digital IF to enable low-power (1.3 mW) and low-voltage (0.6 V) operation. Implemented in 65 nm CMOS, this work is compatible with the IEEE 802.15.6 (WBAN) narrowband physical layer speci fication a nd achieves 91 dBm and 96 dBm sensi- tivity at 10 BER for -DQPSK and -DBPSK modulation respectively. The proposed highly digital architecture and supply voltage scaling le ad to a 3x improvement in RX energy ef ficiency and minimize silicon area consumption ( 0.35 mm in 65 nm CMOS) while achieving state-of-the-art sensitivity. While this implementation focuses on WBAN demodulation, the proposed architecture and circuit technique s are generally applicable to RX targeting ultra-low power consumption for sensor networks.