Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS

Abstract

A continuous-time 7-tap FIR equalizer tailored to dispersion compensation in multi-mode fiber links is presented. By using a novel active delay line, the ultra-compact equalizer is very flexible, maintaining optimal performances and power scalability over a wide range of input data-rates. Particular care is taken to address critical issues of continuous-time realizations, such as noise, linearity and dynamic r ange. All-pass stages, realized with a simple circuit topology featuring high linearity and wide bandwidth, are investigated to implement the active delay line elements. Filter tap coef ficients are realized with programmable transconductors and output curr ents are summed through a tran- simpedance ampli fier, providing simultaneously high gain and wide bandwidth. Extensive experimental results, carried out on test chips realized in 28 nm LP CMOS technology, are presented. The equalizer demonstrates succ essful operation with variable data-rates ranging from 10 Gb/s t o 25 Gb/s and power dissipation scalable from 55 mW to 90 mW. Compared to previously reported high-speed FIR equalizers, the p r o p o s e ds o l u t i o na c c e p t st h e largest variation of the input data-rate with state-of-the-art power efficiency and core silicon area of only 0.085 mm , meeting the demand of emerging 400 Gb/s standards.