← 返回 JSSC 论文列表JSSC 2014第12期Digital Circuits0.35 µmNeural Network Accelerator
CMOS Impedance Analyzer for Nanosamples Investigation Operating up to 150 MHz With Sub-aF Resolution Davide Bianchi, Student Member , IEEE
提出一种新型CMOS阻抗分析器，用于纳米样品研究，工作频率高达150 MHz。
0.35 µm CMOS, 1 kHz–150 MHz, 0.4 aF分辨率
CMOS阻抗分析器纳米样品高带宽高灵敏度
▸创新点1：采用双通道调制/放大/解调结构嵌入反馈环路，实现全工作频率范围内的高环路增益，显著提升系统稳定性和带宽性能（1 kHz至150 MHz）。
▸创新点2：通过新型电路架构克服传统跨阻拓扑的噪声与频率限制，实现输入电容值高达100 pF的稳定性，无需外部锁相环或滤波器。
▸创新点3：直接提供与DUT导纳实部和虚部成比例的两个直流输出，简化系统设计并提高测量效率，输出带宽可调（数十Hz至50 kHz）。
▸创新点4：在0.35 µm CMOS工艺下实现0.4 aF的高分辨率（100 kHz–150 MHz范围，Vin = 1 V，BW = 50 Hz），适用于纳米级样品研究。
Abstract
This work addresses the emerging need for investi- gating micro- and nano-devices by performing Impedance Spec- troscopy with high-sensitivity yet at high bandwidth. To this goal a new circuital architecture has been implemented that overcomes the limitations of the classic tran simpedance topology of noise and maximum operating frequency t rade-off as well as of input ca- pacitance stability concerns. Thanks to a two channel modulation/ amplification/demodulation structure embedded into a feedback loop, high loop gain at all the wor king frequencies is obtained. Implemented in 0.35 µm CMOS, the IC works from 1 kHz up to 150 MHz, independently of the input capacitance value up to about 100 pF. The IC shows a resolution as good as 0.4 aF in the 100 kHz–150 MHz range (Vin = 1 V , BW = 50 Hz). The circuit directly provides two DC outputs proportional to the Real and Imaginary component of the DUT admittance so that no external lock-in structure or filter is required. The output bandwidth is ad- justable from few tens of Hz up to 50 kHz, thus allowing both fast impedance tracking and high resolution impedance spectroscopy.