Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier

Abstract

An antenna load impedance detection and a utomatic tuning technique is presented. An antenna load impedance detec- tion circuit as well as burst detector enabling autonomous tuning is integrated on a CMOS-PA chip. A low-loss impedan ce tuner with an SOI switch is also demonstrated. The proposed impedance de- tection circuit employs polar det ection technique, so that the an- tenna impedance is tuned in a vector fashion to track the time- varying antenna impedance prom ptly. Also, it can operate with nonconstant envelope signal thanks to an introduced relative de- tection technique. At the back-off ope ration, the impedance can be automatically tuned to optimum value. The circuit is time shared with PA linearization loop, minimizing the overhead of the cir- cuit. When the VSWR is approximately 2.5, the peak PAE is kept more than 40% with tuning, whereas it varies from 28% to 45% without tuning. The linear ef ficiency without the tuning is 15% as the worst case, while more than 30% of PAE is maintained when the tuning and PA-closed loop are enabled. The drain ef ficiency at 6 dB back-off is improved from 30% to 40%. The tuner can cover a VSWR of around 6, while achie ving a loss ranging from 0.3 to 4.6 dB.