JSSC 2015第1期Memory14nmSRAM

A 14 nm FinFET 128 Mb SRAM With V Enhancement Techniques for Low-Power Applications Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Y ang, Jaeho Park, Sunghyun Park, Y ongho Kim, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sun gbong Kim, Gyuhong Kim, Jintae Kim, Y oungkeun Lee, Sang-Pil Sim, Jong Shik Y oon, K yu-Myung Choi, Hyosig Won, and

14纳米FinFET技术下的128Mb SRAM芯片，采用负位线方案和降噪技术提升性能与能效。

14 nm FinFET, 128 Mb, 0.50 V with 200 mV improvement by NBL, 0.47 V with 40 mV improvement by DNR

SRAMFinFET低功耗写入辅助读取辅助

▸创新点1：负位线方案（NBL）作为写入辅助技术，通过动态调整位线电压至负值（-200 mV）显著提升写入稳定性，在14 nm FinFET工艺下实现0.50 V的最低工作电压，较传统方案降低45.4%功耗（电路创新）

▸创新点2：降噪技术（DNR）作为读取辅助电路，采用动态噪声抑制机制减少位线扰动，使高性能SRAM（6T-HP）工作电压降至0.47 V，噪声容限提升40 mV，功耗降低12.2%（电路创新）

▸创新点3：双电源供电架构设计，针对高密度（HD）与高性能（HP）应用分别优化供电电压，HD模式采用0.064 μm² bitcell实现高存储密度，HP模式通过0.080 μm² bitcell提升速度（系统级创新）

▸创新点4：FinFET工艺适配技术，在14 nm节点下优化6T SRAM bitcell的鳍式晶体管布局，兼顾泄漏电流控制与驱动能力，使128 Mb大容量阵列在亚0.5V电压下稳定工作（工艺创新）

Abstract

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 m and a 0.080 m 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 with 200 mV improvement by NBL, and 0.47 for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.