JSSC 2015第1期Wireline I/O22nmDRAM

A 1 Gb 2 GHz 128 GBs Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology F

22纳米三栅CMOS技术中实现的1Gb 2GHz嵌入式DRAM，具有128GB/s带宽

1Gb容量, 2GHz频率, 128GB/s带宽, 1.05V电压, 100µs保持时间

嵌入式DRAM三栅CMOS高k金属栅MIM电容器多芯片封装

▸采用三栅高k金属栅晶体管和MIM电容器

▸集成可编程电荷泵实现字线过驱动和欠驱动

▸多芯片封装技术提升图形处理性能

Abstract

An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology usin g tri-gate high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed, which includes fully in tegrated programmable charge pumps to over- and underdrive w ordlines with output voltage regulation. The die area is 77 mm and provides 64 GB/s Read and 64 GB/s Write at 1.05 V. 100 µs retention time is achieved at 95°C using the worst case memory array stress patterns. The 1 Gb eDRAM die is multi-