A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Abstract

A 16 × 16 mesh network-on-c hip (NoC) is fabricated in 22 nm tri-gate CMOS for high-throughput, energy-ef ficient on-chip interconnect in multi-core processors and systems-on-chip. The NoC connects 256 nodes that are each in their own voltage and clock domain using 5-port routers and 112 b, 855 µm data links. Source-synchronous operati on eliminates global clock dis- tribution power and adapts to process, voltage, and temperature variations. Hybrid packet/circu it switching improves energy efficiency by removing intra-rout e data storage and increases throughput with parallel packet-switched channel setup and circuit-switched data transfer. The NoC achieves: i) 20.2 Tb/s total throughput at 0.9 V , 25 °C; ii) source-synchronous operation for a 2.7× increase in bisection bandwidth to 2.8 Tb/s and 93% r e d u c t i o ni nc i r c u i t - s w i t c h e dlatency at 407 ps/hop, compared to synchronous design; iii) hybrid packet/circuit switching for a 62% latency improvement and 55% increase in energy ef ficiency to 7.0 Tb/s/W, compared to packet switching; iv) a peak energy efficiency of 18.3 Tb/s/W for near-threshold operation at 430 mV , 25 °C; v) ultra-low-voltage operation down to 340 mV , 25 °C, with router power scaling to 363 µW.