A 6 mW 5000-Word Real-Time Speech Recognizer Using WFST Models

Abstract

We describe an IC that provi des a local speech recog- nition capability for a variety of electronic devices. We start with a generic speech decoder architecture that is programmable with in- dustry-standard WFST and GMM speech models. Algorithm and architectural enhancements are incorporated in order to achieve real-time performance amid syste m-level constraints on internal memory size and external memory bandwidth. A 2.5 × 2.5 mm test chip implementing this architecture was fabricated using a