A Multi-Granularity FPGA With Hierarchical Interconnects for Ef ficient and Flexible Mobile Computing Fang-Li Y uan, Student Member , IEEE , Cheng C. Wang , Student Member , IEEE , Tsung-Han Y u, Student Member , IEEE, and Dejan Markovi ć, Member , IEEE

Abstract

Following the rapid expansion of mobile computing, mobile system-on-a-chip (SoC) designs have off-loaded most compute-intensive tasks to dedicated accelerators to improve energy and area ef ficiency. An increasing number of acceler- ators in power-limited SoCs results in large regions of “dark silicon.” Unlike processors, dedicated hardware is in flexible, so any changes would require a chip re-design, which signi ficantly impacts cost and timeline. To address the need for ef ficiency and flexibility, this work presents a multi-granularity FPGA suitable for mobile computing. Occupying 20.5 mm in 40 nm CMOS, the chip incorporates fine-grained con figurable logic blocks, medium-grained DSP processors and recon figurable block RAMs, and two coarse-grained kernels: a 64- to 8192-point FFT processor and a 16-core universal DSP for software-de fined radios. Using a mix-radix hierarchical interc onnect, the chip achieves a 3–4x interconnect area reduction over commercial FPGAs for compa- rable connectivity, reducing overall area and leakage by 2–2.5x, and delivering up to 50% lower active power. With coarse-grained kernels, the energy efficiency reaches within 4–5x of ASIC designs.