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Steamroller Module and Adaptive Clocking System in 28 nm CMOS Kathryn Wilcox Me
介绍AMD Steamroller模块及自适应时钟系统在28nm CMOS工艺中的物理设计实现。
28nm CMOS, 29.47mm², 236 million transistors
AMD Steamroller自适应时钟28nm CMOS物理设计功耗效率
▸Steamroller模块设计
▸自适应时钟系统
▸从32nm SOI到28nm Bulk CMOS的设计挑战
Abstract
This work describes the physical design implemen-
tation of the AMD “Steamroller” module and adaptive clocking
system that are both integral pieces of the AMD Kaveri APU SoC
which was implemented using a 28 nm high-K metal gate Bulk
CMOS process. The Steamroll er module occupies 29.47 mm
and
contains 236 million transistors. Various aspects of the core design
are covered including the power and timing methodologies as well
as design challenges moving from 32 nm SOI to 28 nm Bulk CMOS.
Adaptive c