The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated V oltage Regulation, and Resonant Clocking Eric J. Fluhr , Member , IEEE, Steve Baumgartner, David Boe rstler, John F. Bulzacchelli , Member , IEEE, Timothy Diemoz, Daniel Dreps, George En glish, Joshua Friedrich

Abstract

POWER8™ is a 12-core processor fabricated in IBM’s 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket perfor- mance over POWER7+™. Core throughput is supported by 7.6 Tb/s of off-chip I/O bandwidth which is provided by three primary interfaces, including two new variants of Elastic Interface as well as embedded PCI Gen-3. Power ef ficiency is improved with several techniques. An on-chip c ontroller based on an embedded PowerPC™ 405 processor applies per-core DVFS by adjusting DPLLs and fully integrated voltage regulators. Each voltage regulator is a highly distributed system of digitally controlled microregulators, which achieves a peak power ef ficiency of 90.5%. A wide frequency range resonant clock design is used in 13 clock meshes and demonstrates a minimum power savings of 4%. Power and delay ef ficiency is achieved through the use of pulsed-clock latches, which require statistical validation to ensure robust yield.