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Three-Dimensional 128 Gb MLC V ertical NAND Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming Ki-Tae Park, Sangwan Nam, Daehan Kim, Pansuk Kwa k, Doosub Lee, Y oon-He Choi, Myung-Hoon Choi, Dong-Hun Kwak, Doo-Hyun Kim, Min-Su Kim, Hyun-Wook Park, Sang-Won Shim, Kyung-Min Kang, Sang-Won Park, Kangbin Lee, Hyun-Jun Y oon, Kuihan Ko, Dong-Kyo Shim, Y ang-Lo Ahn, Jinho Ryu, Donghyun Kim, Kyunghwa Y un, Joonsoo Kwon, Seunghoon Shin, Dae-Seok Byeon, Kihwan Choi, Student Member , IEEE, Jin-Man Han, Kye-Hyun Kyung, Jeong-Hyuk Choi, and
首次实现128Gb 3D垂直NAND闪存，采用环绕栅极结构和屏障工程材料，优化编程分布与功耗。
50MB/s写入吞吐量，3K次耐久性（嵌入式应用）；35K次耐久性，36MB/s写入吞吐量（数据中心应用）
3D NAND垂直闪存环绕栅极屏障工程高电压保护
▸创新点1：采用屏障工程材料和环绕栅极结构（方法创新），通过优化材料能带结构和全环绕栅设计，显著减小了阈值电压漂移和自然分布宽度，提升了存储单元的稳定性和可靠性。
▸创新点2：负反脉冲方案实现紧密编程分布（电路创新），通过精确控制编程脉冲的负向补偿，有效压缩了单元阈值电压分布范围，提高了多级存储的精度和一致性。
▸创新点3：大WL耦合效应的抵消放电方案（系统创新），采用纹波消除放电技术和预偏移控制策略，降低了字线间寄生耦合干扰，确保高速读写时的信号完整性。
▸创新点4：外部高压供电与保护机制（系统创新），集成高效高压生成电路和故障防护设计，在降低功耗的同时实现50MB/s写入吞吐量及3K/35K耐久性扩展。
Abstract
In this work, we present a true 3D 128 Gb 2 bit/cell vertical-NAND (V-NAND) Flash product for the first time. The use of barrier-engineered materia ls and gate all-around structure in the 3D V-NAND cell exhibits advantages over nm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution . Also, a negative counter-pulse scheme realizes a tightly programmed cell distribution. In order to reduce the effect of a large WL coupling, a glitch-canceling discharge scheme and a pre-offset control scheme is implemented. Furthermore, an external high- voltage supply scheme along with the proper protection scheme for a high-voltage failure is used to achieve low power consumpti on. The chip accomplishes 50 MB/s write throughput with 3 K e ndurance for typical embedded applications. Also, extended en durance of 35 K is achieved with 36 MB/s of write throughput for data center and enterprise SSD applications.