A Decision-Error-Tolerant 45 nm CMOS 7b 1 GSs Nonbinary 2bCycle SAR ADC Hyeok-Ki

Abstract

A compact decision-error-tolerant 2b/cycle SAR ADC architecture is presented. Two DACs with different desi g- nated functions, SIG-DAC an d REF-DAC, are implemented to make the structure compact and to eliminate the sampling skew issue. Use of a nonbinary decision scheme with deci sion redundan- cies not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robust to reference fluctuations and comparator offset variations. The proposed dynamic registe