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A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating Y
65nm CMOS工艺下实现的全并行非二进制LDPC解码器，支持动态时钟门控，吞吐量达1.22Gb/s。
65nm CMOS, 1.0V/675mV, 700MHz/400MHz, 1.22Gb/s/698Mb/s, 3.03nJ/b/89pJ/b/iteration
非二进制LDPC全并行解码器动态时钟门控能效优化GF(64)
▸全并行架构降低布线开销
▸一步前瞻校验节点设计提升时钟频率至700MHz
▸动态时钟门控和提前终止机制提高能效
Abstract
Nonbinary LDPC (NB-LDPC) codes, defined over
Galois field, offer better coding gain and a lower error floor
than binary LDPC codes. However, the complex decoding and
large memory requirement have prevented any practical chip
implementations. We presen t a 1.22 Gb/s fully parall el decoder of
a GF(64) (160, 80) regular-(2, 4) NB-LDPC code in 65 nm CMOS.
The reduced number of edges in NB-LDPC code's factor graph
permits a low wiring overhead in the fully parallel architecture.
The throughput is furth