A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating Y oun

Abstract

Nonbinary LDPC (NB-LDPC) codes, defined over Galois field, offer better coding gain and a lower error floor than binary LDPC codes. However, the complex decoding and large memory requirement have prevented any practical chip implementations. We presen t a 1.22 Gb/s fully parall el decoder of a GF(64) (160, 80) regular-(2, 4) NB-LDPC code in 65 nm CMOS. The reduced number of edges in NB-LDPC code's factor graph permits a low wiring overhead in the fully parallel architecture. The throughput is further impr oved by a one-step look-ahead check node design that increases the clock frequency to 700 MHz, and the interleaving of variable node and check n ode operations that shortens one decod ing iteration to 47 clock cycles. We allow each processing node to detect its own convergence and apply dynamic clock gating to save power. When a ll processing nodes have been clock gated, the deco der terminates and continues with the next input to increase the throughput to 1.22 Gb/s. The dynamic clock gating and decoder termi nation improve the energy efficiency to 3.03 nJ/b, or 259 pJ/b/iteration, at 1.0 V and 700 MHz. Voltage scaling to 675 mV improves the energy efficiency to 89 pJ/b/iteration for a throughput o f 698 Mb/s at 400 MHz.