← 返回 JSSC 论文列表JSSC 2015第2期Data Converters65nmDelta-Sigma ADCPLL
A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2835 GHz DCO
首款基于二阶频率数字转换器(FDC)的全集成数字分数PLL，替代传统TDC方案
65nm CMOS, 0.56mm², 21mW@1.0/1.2V, 123dBc/Hz@1MHz
频率数字转换器分数PLL数字环路滤波器开关电容DCO相位噪声
▸采用FDC替代TDC实现量化噪声高通滤波
▸数字环路滤波器对模拟非理想行为不敏感
▸新型抗电源噪声的开关电容DCO频率控制结构
Abstract
This paper presents the first published fully-in-
tegrated digital fractional- PLL based on a second-order
frequency-to-digital converter ( FDC) instead of a time-to-digital
converter (TDC). The PLL's quantization noise is nearly identical
to that of a conventional analog delta-sigma modulator based
PLL (
-PLL). Hence, the quantization noise is highpass shaped
and is suppressed by the PLL's loop filter to the point where it
is not a dominant contributor to the PLL's output phase noise.
However, in