Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-V ector Prediction

Abstract

A magnetic tunnel junction (MTJ)-based logic-in- memory hardware accelerator LSI with cycle-based powe r gating is fabricated using a 90 nm MTJ /MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ de vice model produced by the fabricated test chips. Thr ough the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine tempor al granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic- in-memory.