← 返回 JSSC 论文列表JSSC 2015第3期RF & Wireless65nm
A 32–48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology
65nm CMOS工艺下采用多相位序列化技术的3.248Gbs高效能发射器
65nm CMOS, 1.2V, 32-48Gb/s, 0.4mm², 88mW, 1.8pJ/bit
发射器多相位序列化注入锁定振荡器高速多路复用能效优化
▸创新点1：多相位序列化器，通过多相位时钟信号实现高效数据序列化，显著降低时序约束，提升传输速率至3248 Gb/s。
▸创新点2：基于注入锁定振荡器的多相位分频器，采用注入锁定技术实现宽范围频率分频，支持32至48 Gb/s的数据速率范围。
▸创新点3：高速多路复用结构，优化时序路径设计，减少信号延迟，实现接近1 FO-4门延迟的比特时间，提升整体系统效率。
▸创新点4：采用65 nm CMOS工艺，仅使用标称器件实现高性能，芯片面积仅0.4 mm²，功耗低至1.8 pJ/bit，显著提升能效比。
Abstract
A power-efficient transmitter is proposed using a mul- tiphase serializer, multiphase dividers using injection-locked oscil- lators, and a high-speed multiplexing structure to relax the timing constraints. With this architecture, bit times near 1 FO-4 gate delay are achieved using only nominal devices in a 65 nm CMOS technology. The divider and serializer operate over a wide range of data rates between 32 and 48 Gb/s limited mainly by the opera- tion range of the frequency synth esizer. The transmitter occupies 0.4 mm and consumes 88 mW from a 1.2 V supply which corre- sponds to 1.8 pJ/bit of power efficiency.