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A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS
40nm CMOS工艺下实现的高带宽、高能效两步VCO型Delta-Sigma ADC
40nm CMOS, 0.9V, 1.6GHz采样率, 40MHz带宽, 59.5dB SNDR, 67.7dB SFDR, 2.57mW功耗
VCO型ADCDelta-Sigma调制器失真消除动态元件匹配能效优化
▸开环结构和高数字化模块设计
▸粗/细VCO量化器非线性失真消除技术
▸利用VCO量化器固有DEM特性降低DAC单元匹配要求
Abstract
A 40 MHz-BW 10 bit two-step VCO-based Delta-Sigma ADC is presented. With the open-loop structure and highly digital building blocks, a robust performance, high band- width and high power efficiency are achieved. The nonlinearities of the coarse and the fine VCO-bas ed quantizers are mitigated by distortion cancellation and voltage swing reduction schemes respectively. Because of the i ntrinsic DEM of the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. The experimental results in 40 nm CMOS show that, with 1.6 GHz sampling frequency, the proposed ADC reaches 59.5 dB SNDR and 67.7 dB SFDR for 40 MHz bandwidth. The power consumption is only 2.57 mW under 0.9 V power supply, corresponding the best FoM (42 fJ/step) among high bandwidth ( 20 MHz) DS ADCs.