← 返回 JSSC 论文列表JSSC 2015第3期Data Converters40nmDelta-Sigma ADC
A 42 fJStep-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS
40nm CMOS工艺下实现的高带宽、高能效两步VCO型Delta-Sigma ADC
40nm CMOS, 0.9V, 1.6GHz采样率, 40MHz带宽, 59.5dB SNDR, 67.7dB SFDR, 2.57mW功耗
VCO型ADCDelta-Sigma调制器失真消除动态元件匹配能效优化
▸开环结构和高数字化模块设计
▸粗/细VCO量化器非线性失真消除技术
▸利用VCO量化器固有DEM特性降低DAC单元匹配要求
Abstract
A 40 MHz-BW 10 bit two-step VCO-based
Delta-Sigma ADC is presented. With the open-loop structure and
highly digital building blocks, a robust performance, high band-
width and high power efficiency are achieved. The nonlinearities
of the coarse and the fine VCO-bas ed quantizers are mitigated
by distortion cancellation and voltage swing reduction schemes
respectively. Because of the i ntrinsic DEM of the VCO-based
quantizer output, the matching requirement of the DAC cells is
greatly relaxed. The