← 返回 JSSC 论文列表JSSC 2015第3期RF & Wireless90nmCDRNeural Network Accelerator
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energ
一种具有可编程输入抖动滤波功能的突发模式数字接收器,实现快速开关操作和能量比例链路。
90nm CMOS, 2.2 Gb/s, 6.1 mW, 2.77-3.87 pJ/bit, 36 mV输入灵敏度
突发模式接收器数字时钟数据恢复能量比例链路抖动滤波CMOS
▸通过将输入数据边沿注入到振荡器中,实现瞬时相位锁定和输入抖动滤波
▸结合前馈和反馈架构的优势,实现能量比例操作
▸通过控制注入振荡器的数据边沿数量,精确控制抖动传递带宽和抖动容忍转角
Abstract
A full-rate burst-mode receiver that achieves fast
on/off operation needed for energy-proportional links is presented.
By injecting input data edges into the oscillator embedded in a
classical Type-II digital clock and data recovery (CDR) circuit,
the proposed receiver achieves i nstantaneous phase-locking and
input jitter filtering simultaneously. In other words, the proposed
CDR combines the advantages of c onventional feed-forward and
feedback architectures to achieve energy-proportional opera