A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links Woo-Seok Choi , Student Member , IEEE , Tejasvi Anand , Student Member , IEE E, Guanghua Shu , Student Member , IEEE,A m r E l s h a z l y, Member , IEEE, and Pavan

Abstract

A full-rate burst-mode receiver that achieves fast on/off operation needed for energy-proportional links is presented. By injecting input data edges into the oscillator embedded in a classical Type-II digital clock and data recovery (CDR) circuit, the proposed receiver achieves i nstantaneous phase-locking and input jitter filtering simultaneously. In other words, the proposed CDR combines the advantages of c onventional feed-forward and feedback architectures to achieve energy-proportional operation. By controlling the number of data edges injected into the oscil- lator, both the jitter transfer bandwidth and the jitter tolerance corner are accurately controlled. The feedback loop also corrects for any frequency error and helps improve CDR's immunity to oscillator frequency drift durin g the power-on and -off states. This also improves CDR's tolerance to consecutive identical digits present in the input data. Fabricated in a 90 nm CMOS process, the prototype receiver instanta neously locks onto the very first data edge and consumes 6.1 mW at 2.2 Gb/s. Owing to its short power-on time, the receiver's en ergy efficiency varies only from 2.77 pJ/bit to 3.87 pJ/bit when the effective data rate is varied from 0.44 Gb/s to 2.2 Gb/s. Input sensitivity of the receiver is 36 mV for a BER of 10 .