An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS Sebastian Höppner, Dennis Walter, Thomas Hocker, Stephan Henker, Stefan Hänzsche, Daniel Sausner, Georg Ellguth, Jens-Uwe Schlüßler, Holger Eisenreich, and René Schüffny

Abstract

This paper presents a network-on-chip (NoC) SerDes transceiver architecture for long distance interconnects in the mm range within MPSoCs. Its source synchronous clock ing scheme en- ables application in GALS systems and allows completely stop- pable transceiver clocking for low idle power consumption. A ca- pacitive line driver with combined resistive dr iver for well defined DC swing is employed and analyzed in detail by simulation studies. It is shown that proper DC swing definition is mandatory for ro- bust operation of long links at high data r ates. Prototypes of the transceiver over 6 mm bufferless o n-chip interconnect are imple- mented in both 65 nm and 28 nm CMOS technologies. The 65 nm realization achieves an efficiency of 1 73 fJ/bit/mm at 90 Gbit/s at 1.25 V and 93 fJ/bit/mm at 45 Gbit/s low speed mode at 0.9 V. The 28 nm realization achieves 81 fJ/bit/mm at 72 Gbit/s at 1.05 V and 64 fJ/bit/mm at 36 Gbit/s low speed mo de at 0.95 V. The trans- ceiver can be seamlessly integrated as black box point-to-point con- nection into heterogeneous MPSoC NoCs to enable ultra-compact toplevel floorplan realizatio n and increased energy efficiency. An example of a 20-core MPSoC in 65 nm CMOS technology with 10 serial NoC transceivers is presented.