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An Energy Efficient Multi-Gbits NoC Transceiver Architecture With Combined ACDC D
提出一种高效能多Gbits网络芯片收发器架构，适用于MPSoC中的长距离互连。
65nm CMOS 1.25V 90Gbit/s 173fJ/bit/mm, 28nm CMOS 1.05V 72Gbit/s 81fJ/bit/mm
网络芯片收发器能效多核系统长距离互连
▸源同步时钟方案适用于GALS系统
▸可完全停止的收发器时钟以降低空闲功耗
▸结合电阻驱动器的电容性线路驱动器
Abstract
This paper presents a network-on-chip (NoC) SerDes
transceiver architecture for long distance interconnects in the mm
range within MPSoCs. Its source synchronous clock ing scheme en-
ables application in GALS systems and allows completely stop-
pable transceiver clocking for low idle power consumption. A ca-
pacitive line driver with combined resistive dr iver for well defined
DC swing is employed and analyzed in detail by simulation studies.
It is shown that proper DC swing definition is mandator