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JSSC 2015第3期Other160nm

Compact Cascadable g m-C All-Pass True Time Delay Cell With Reduced Delay V ariation

提出一种紧凑可级联的gm-C全通真延时单元,适用于1-2.5 GHz频段,具有低延迟变化和高线性度。
160 nm CMOS, 550 ps最大延迟, 13 ps步进, 1-2.5 GHz频段
gm-C全通滤波器真延时单元CMOS相位线性度时间阵列接收机
创新点1:紧凑可级联的gm-C全通滤波器设计,采用160 nm CMOS工艺,实现了550 ps的最大延迟,延迟面积比提升至少50倍,显著减小了芯片尺寸。
创新点2:5倍频率范围扩展,通过优化gm-C滤波器设计,将工作频率范围扩展至1–2.5 GHz,同时保持增益变化在1 dB以内,提升了宽带性能。
创新点3:延迟变化小于10 ps,通过改进电路技术,实现了RMS延迟变化误差小于10 ps,确保了在宽频带内的延迟稳定性。
创新点4:提出设计方程和非理想性分析,推导了传输函数及多种非理想性的设计方程,为滤波器设计提供了理论支持。
Abstract
At low-GHz frequencies, analog time-delay cells re- alized by LC delay lines or transmission lines are unpractical in CMOS, due to their large size. As an alternative, delays can be ap- proximated by all-pass filters exploiting transconductors and ca- pacitors (g m-C filters). This paper presents an easily cascadable compact gm-C all-pass filter cell for 1–2.5 GHz. Compared to pre- vious gm-RC and g m-C filter cells, it achieves at least 5x larger fre- quency range for the same relative delay variation, while keeping gain variation within 1 dB. This paper derives design equations for the transfer function and several non -idealities. Circuit techniques to improve phase linearity and r educe delay variation over fre- quency, are also proposed. A 160 nm CMOS chip with maximum delay of 550 ps is demonstrated with monotonous delay steps of 13 ps (41 steps) and an RMS delay variation error of less than 10 ps over more than an octave in frequency (1–2.5 GHz). The delay per area is at least 50x more than for earlier chips. The all-pass cells are used to realize a four element timed-array receiver IC. Mea- surement results of the beam pattern demonstrate the wideband operation capability of the g m-RC time delay cell and timed-array IC-architecture.