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340 mV11 V 289 GbpsW 2090-Gate NanoAES Hardware Accelerator With Area-Optimized
一款22纳米三栅极CMOS工艺的纳米AES硬件加速器，具有低功耗和高能效特性。
1.133 GHz最大操作频率，13 mW总功耗，289 Gbps/W能效
AES硬件加速器低功耗CMOS加密
▸使用单8位Sbox电路和ShiftRows字节顺序数据处理
▸串行累积MixColumns电路
▸面积优化的加密和解密Galois域多项式
Abstract
This paper describes an on-die lightweight
nanoAES hardware accelerator, fabricated in 22 nm tri-gate
high-k/metal-gate CMOS, targeted for ultra-low power sym-
metric-key encryption and decryption on mobile SOCs. Compared
to conventional 128 bit AES implementati ons, this design uses
a single 8 bit Sbox circuit along with ShiftRows byte-order
data processing to compute all AES rounds in native
composite-field. This approach along w ith a serial-accumulating
MixColumns circuit, area-optimized encr