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A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band Shiyu Su , Student Member , IEEE, Tu-I Tsai, Praveen Kumar Sharma , Student Member , IEEE,a n d Mike
提出一种12位1GS/s双速率混合DAC，采用8GS/s展开流水线Delta-Sigma架构，实现高动态范围。
12位分辨率，1GS/s Nyquist速率，8GS/s Delta-Sigma速率，91-76 dB SFDR（500 MHz带宽）
混合DACDelta-Sigma调制器噪声整形预失真补偿流水线架构
▸双速率混合架构（Nyquist路径与Delta-Sigma路径结合）
▸Delta-Sigma辅助预失真补偿电流导向单元失配
▸8X展开流水线Delta-Sigma调制器实现高速三阶噪声整形
Abstract
A 12 bit Dual-Rate Hybrid digital-to-analog con- verter (DAC) architecture with a split Nyquist (1 GS/s) and delta-sigma modulator path (8 GS/s) is proposed and imple- mented in 65 nm CMOS. Based on the hybrid architecture, the delta-sigma-assisted pre-distortion scheme compensates for the current steering cell mismatch, which further reduces the analog circuit complexity and area. The proposed 8X unrolled pipeline delta-sigma modulator allows fo r high-speed third-order noise shaping with a digital standar d cell design flow. The measured spurious-free dynamic range achieves 91–76 dB over the 500 MHz Nyquist band. The proposed DAC architecture is mostly digital and hence favors future technology scaling.