JSSC 2015第4期Power Management65nmPLL

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Ampliﬁer-Based TDC Ahmed Elkholy , Student Member , IEEE , Tejasvi Anand , Student Member , IEEE , Woo-Seok Choi , Student Member , IEEE ,A m rE l s h a z l y,M e m b e r, IEEE ,a n d Pavan

一种采用高分辨率TDC和真分数分频器的低噪声宽带数字分数N锁相环。

65nm CMOS, 3.7mW, 4.5GHz输出频率, 3MHz带宽, 490fs积分抖动

数字分数N锁相环时间放大器TDC真分数分频器低噪声宽带

▸创新点1：高分辨率时间放大器TDC（TA-TDC）采用窄范围低功耗设计，实现亚1 ps时间分辨率，显著提升相位检测精度，同时抑制传统BB-PLL的极限环行为，支持更宽的PLL带宽（>3 MHz）。

▸创新点2：真分数分频器结合数字时间转换器（DTC），在时间域直接消除量化噪声，降低对TDC动态范围的需求，从而优化系统噪声性能（<106 dBc/Hz）。

▸创新点3：时间域量化噪声消除技术通过DTC动态补偿分频器相位误差，减少非线性影响，提升跟踪速度与稳定性（集成抖动<490 fs）。

▸创新点4：系统级架构创新整合TA-TDC与DTC协同工作，实现快速建立（settling）与低功耗（3.7 mW），FoM达240.5 dB，为同类分数N-PLL最佳。

Abstract

A digital fractional-N PLL that employs a high resolu- tion TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fract ional divider employs a digital-to-time converter (DTC) to cancel out quan- tization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architectu re adopts a narrow range low-power time-ampliﬁer based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLL si sg r e a t l ys u p p r e s s e d by the TA-TDC, thus permitting wide PLL bandwidth. The pro- posed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behav ior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than 106 dBc/Hz in-band noise and 3 MHz PLL band- width at 4.5 GHz output frequency usi ng 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fs inte- grated jitter. This translates to a FoM of 240.5 dB, which is the best among the reported fracti onal-N PLLs.