← 返回 JSSC 论文列表JSSC 2015第4期Clocking & PLLs65nmPLLVCO
A Calibration-Free Fractional-N Ring PLL Using Hybrid PhaseCurrent-Mode Phase In
提出混合相位/电流模式相位插值器(HPC-PI)以提升基于环形振荡器的分数N锁相环相位噪声性能。
65nm CMOS, 4.25至4.75GHz, 104 dBc/Hz带内相位噪声, 1.5 ps集成抖动, 2.4 mW/GHz能效, FoM 225.8 dB
分数N锁相环相位噪声环形振荡器相位插值器带宽扩展
▸混合相位/电流模式相位插值器(HPC-PI)
▸XOR相位检测器/插值器(XOR PD-PI)块实现精确量化误差消除
▸数字MDLL前置以扩展带宽
Abstract
A hybrid phase/current-mode phase interpolator
(HPC-PI) is presented to impr ove phase noise performance of
ring oscillator based fractio nal-N PLLs. The proposed HPC-PI
alleviates the bandwidth trade-off between VCO phase noise sup-
pression and
quantization noise suppression. By combining
the phase detection and interpolation functions into XOR phase
detector/interpolator (XOR PD-PI) block, accurate quantization
error cancellation is achieved without using calibration. Use of a
digital MDLL in