A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction

Abstract

Hardware-based computer vision accelerators will be an essential part of future mobile devices to meet the low power and real-time processing requirement. To realize a high energy ef- ficiency and high throughput, the accelerator architecture can be massively parallelized and tailored to vision processing, which is an advantage over software-based s olutions and general-purpose hardware. In this work, we present an ASIC that is designed to learn and extract features from images and videos. The AS