Dynamic Architecture and Frequency Scaling in 0812 GSs 7 b Subranging ADC Kentar

Abstract

Dynamic Architecture and Frequency Scaling (DAFS) is shown to realize superlinear power scaling in high-speed analog-to-digital converters (A DCs). To achieve both high-speed operation and low power consum ption, the ADC architecture is reconfigured between binary sear ch and flash every clock cycle, relying on the conversion delay. The proposed binary search/flash architecture reconfigurable ADC can be implemented with only a small modification to conventional binary search ADCs. By live configuring,