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A 92127 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS
28nm CMOS工艺下实现的高性能分数分频子采样锁相环，具有低相位噪声和宽调谐范围。
28nm CMOS, 0.9V/1.8V供电, 13mW功耗, 280fs RMS抖动, -104dBc/Hz带内相位噪声
分数分频锁相环子采样数字时间转换器相位噪声CMOS
▸采用10位0.55 ps/LSB数字时间转换器（DTC）实现分数分频
▸背景校准技术降低DTC增益误差和杂散
▸类B型VCO实现9.2-12.7GHz宽调谐范围
Abstract
This paper describes a frac tional-N subsampling
PLL in 28 nm CMOS. Fractional phase lock is made possible with
almost no penalty in phase noise performance thanks to the use
of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit
operating on the sampling clock. The performance limitations of
a practical DTC implementation a re considered, and techniques
for minimizing these limitations are presented. For example,
background calibration guarantees appropriate DTC gain, re-
ducing spurs