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JSSC 2015第5期RF & Wireless65nmNeural Network Accelerator

A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching Anders Nejdel , Student Member , IEEE , Henrik Sjöland , Senior Member , IEE E,a n d Markus Törmänen , Senior Member , IEEE

一种采用噪声消除技术的无电感频率选择性输入匹配无线接收器前端,工作频率0.7至3.8 GHz。
65nm CMOS, 1.2V, 22.8–34.9 mA, 噪声系数1.6-3.2 dB, IIP2 > +75 dBm, IIP3 > +1 dBm
无线接收器噪声消除频率选择性CMOS负反馈
创新点1:无电感频率选择性输入匹配(电路创新)。该设计通过负反馈机制实现频率选择性输入匹配,避免了传统电感匹配的复杂性和面积开销,显著减小了芯片面积并提高了设计灵活性。
创新点2:噪声消除技术(系统创新)。引入辅助路径并采用数字可控增益,有效消除了主路径的噪声,同时保持了高线性度,实现了1.6 dB至3.2 dB的低噪声系数。
创新点3:负反馈降低输入阻抗(电路创新)。通过将输出电流反馈到主路径输入端,显著降低了输入阻抗,实现了宽带范围内的输入匹配,覆盖0.7 GHz至3.8 GHz的频率范围。
创新点4:高线性度设计(系统创新)。通过优化电路结构和反馈机制,实现了+75 dBm的IIP2和+1 dBm的IIP3,显著提升了接收器的抗干扰能力和动态范围。
Abstract
This paper presents an inductor-less frequency selec- tive input match wireless receiver front-end utilizing noise cancel- lation, operational from 0.7 to 3.8 GHz. The main path of the re- ceiver consists of a high input impedance transconductance stage where the output is down-converted to baseband by current mode passive mixers, and then amplified to voltage by a transimpedance amplifier. The output voltage is converted into a current and fre- quency up-converted by a second set of transconductance stage and mixer. This current is then fed back to the input of the main path, reducing the input impedance, providing input match by means of negative feedback. An auxiliary path with digitally controllable gain is also introduced to cancel the noise of the main path while maintaining high linearity. The chip prototype is fabricated in a 65 nm CMOS process and occupies an active area of 0.15 mm .I t achieves a noise figure between 1.6 dB and 3.2 dB depending on the frequency of operation, and an out-of-band IIP2 and IIP3 better than +75 dBm and +1 dBm, respect ively. The chip is supplied by 1.2 V and consumes 22.8–34.9 mA.