JSSC 2015第5期Clocking & PLLs65nmDLL

Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power

提出一种基于漏电流的数字控制振荡器和快速重锁MDLL，用于超低功耗传感器平台。

65nm CMOS, 423nW@3.2MHz, FoM=0.132nW/MHz

超低功耗数字控制振荡器漏电流MDLL快速重锁

▸创新点1：基于漏电流的数字控制振荡器（电路创新）。该论文提出了一种新型数字控制漏电流振荡器，利用晶体管的亚阈值漏电流作为振荡源，实现了423nW的超低功耗和3.2MHz的频率输出，相比传统振荡器显著降低了功耗。

▸创新点2：RC模型分析与验证（方法创新）。作者将漏电流振荡器建模为RC振荡器并进行了理论分析，通过仿真验证了模型的准确性，为超低功耗振荡器设计提供了新的分析方法。

▸创新点3：自适应快速频率重锁方案（系统创新）。MDLL采用了一种智能重锁机制，能够根据休眠状态下的频率漂移量自适应选择最优锁定过程，大幅提高了唤醒速度和能效，FoM达到0.132pJ/MHz。

▸创新点4：全数字MDLL架构（系统创新）。整个系统采用全数字设计，在65nm CMOS工艺中实现，结合数字控制漏电流振荡器和快速重锁方案，为超低功耗传感器平台提供了完整的频率生成解决方案。

Abstract

This paper presents an all-digital multiplying delay-locked loop (MDLL) with a leakage-based oscillator for u l t r a - l o w - p o w e rs e n s o rp l a t f o r m s .T h ep r o p o s e dd i g i t a lc o n t r o lo f channel leakage current achieved ultra-low-power consumption in frequency generation with a ﬁne resolution. The leakage based oscillator was modeled as an RC-based oscillator, analyzed, and the analyses were veriﬁed by simulation. The proposed oscillator was applied to the MDLL with a fast frequency relocking scheme which adaptively performs an optimal lock process according to the amount of frequency drift during the sleep state. The MDLL was implemented in 65 nm CMOS and consumed 423 nW for 3.2 MHz generation, and had an energy efﬁciency FoM of 0.132 W/MHz.